The size of semiconductors and the distances between them are rapidly shrinking as technology advances. As a result, SRAM cells used in aerospace applications become more susceptible to soft-error when the fundamental charge of the fragile nodes decreases. Single-event upsets (SEUs)may cause data inversion if a radiation particle hits a sensitive node in a typical 6T SRAM cell.To lessen the impact of SEUs, this paper proposes a Soft-Error-Aware Read-Stability-EnhancedLow-Power12T (SARP12T) SRAM cell. SARP12T's performance is evaluated in relation to those of other recently released soft-error-aware SRAM cells such as QUCCE12T, QUATRO12T,RHD12T, RHPD12T, and RSP14T. Even if the values of the sensitive nodes in SARP12T areflipped due to a radiation attack, the data may be recoverable. SARP12T is resilient to storagenode-pair-initiated single-event multi-node upsets (SEMNUs). The '0' storing memory nodes in the proposed cell are easily accessible through the bit line during read operation and are highly resistant to interruptions. SARP12T is also the most efficient method of holding in terms of energy consumption. SARP12T out performs competing cells in terms of write performance, and its write latency is much lower. The suggested cell achieves all of these advantages with just a little increase in read latency and read/write energy.

Aerospace, SARP12T,QUCCE12T, SRAM