Volume 20 No 12 (2022)
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A Sub-Quadratic Multiplier for ECC Processor in GF (2283)
Sumit Singh Dhanda, Brahmjit Singh and Poonam Jindal
Scalar multiplication decides the performance of elliptic curve processors (ECP). Its efficiency is dependent upon the size and speed of finite-field multipliers. Sub-quadratic multipliers can be used to achieve higher performance of scalar multiplication ECP. In this work, we have proposed a hybrid Karatsuba multiplier for GF(2283) which is coded in Verilog and synthesized on Xilinx PlanAhead software. It is implemented on different Xilinx FPGAs for the detailed analysis. Virtex-6 FPGA is found to be the best for the implementing this design. Implementation has achieved a delay of 8.764 ns and slice consumption of 7532 for this design. On comparison, with existing bit-parallel multipliers, it is verified that the space complexity of the multiplier is less. The design exhibits the minimum delay of 8.041 ns on Virtex-7.
Hybrid-Karatsuba Multiplier; Elliptic Curve Cryptography (ECC); Field-Programmable Gate Array (FPGA); Subquadratic multiplier; Galois field
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