Binary multipliers are essential components of computational systems used in Digital Signal Processing (DSP) and Fast Fourier transform (FFT) applications. Multipliers are important mathematical units that need more hardware resources and processing time. As a result, significant research has been conducted in order to reduce processing time and hardware needs. The Grouping and Decomposition (GD) multiplier is proposed as a high-speed binary multiplier in this research report to save processing time. The primary goal of the proposed multiplier is to improve algorithm processing efficiency in comparison to existing multiplier architectures. The aforementioned goal is attained by employing two methodologies: parallel grouping of partial products of identical size and decomposition of each partial-product bit within the grouped sets. A 5:2 logic adder, often known as a 5LA, is used to perform the summing. The use of parallel processing and decomposition logic reduces the number of computational steps, improving the efficiency of multiplication operations. The proposed GD multiplier's front-end and physical design implementation was carried out in the 180 nm technology library utilizing the Cadence® Virtuoso and Cadence® Virtuoso Assura tools. In compared to established multiplier architectures, the front-end design of the 8 8 suggested GD multiplier demonstrated a considerable reduction in computing time of roughly 56% and a reduction in power-delay product of 53%. The suggested multiplier's power-delay product is additionally reduced by the physical design implementation, which includes using the shortest-path method for internal subsystem routing. When used for increasingly complex multiplication jobs, the proposed multiplier's efficacy increases, making it ideal for advanced applications.

digital signal processing; fast Fourier transform; grouping and decomposition multiplier; 5:2 logic adder