The need for more processing power is always present for digital signal processors (DSPs), especially when it comes to packing more CPU cores into a single integrated circuit. Many tasks that primarily need multiplication and repeated addition are carried out by DSPs, such as convolution, transformation, correlation, and filtering. In DSPs, the Multiply and Accumulate unit (MAC) is crucial, highlighting the necessity of high-performance procedures inside this unit. DSP algorithms rely significantly on the MAC's speed performance. Bit-parallel computing techniques have historically been used to implement MAC architecture; however, as bit precision rises, these techniques lead to quadratic increases in hardware needs. On the other hand, bit-serial computing makes hardware proportionate to bit precision by serializing a single input. This lowers hardware demands. Static power dissipation is also a critical issue as technology advances. This study presents a high-speed MAC unit designed for arithmetic applications, based on the Sequential Finite-Field Multiplier (SFFM) approach. The high-speed pipelined adder architecture is used in the design of the adder blocks inside the MAC unit.

Multiply and Accumulate unit, Digital signal processors, Sequential Finite-Field Multiplier, High-Speed Processing, Pipelined Adder.