


Volume 20 No 4 (2022)
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BURST-ERROR DETECTION AND CORRECTION USING PARALLEL DECODING
Mr. A. Shravan Kumar, Dr. D. Karunakar Reddy
Abstract
Burst errors and clustered errors have become more common in many types of memories as technologies evolves. Clustered errors are caused by a variety of causes, including multiple bit upsets caused by particle impacts, write disturbance errors, and magnetic field coupling. In this paper, a new class of single burst error correcting codes are presented which correct a single burst of any size b within a codeword. A code construction methodology is presented which enables us to construct the proposed scheme from existing codes, e.g., Hamming codes. A new single step decoding methodology for the proposed class of codes is also presented which enables faster decoding. Different code constructions using Hamming codes and BCH codes have been presented in this paper and a comparison is made with existing schemes in terms of decoding complexity and data redundancy. The proposed scheme in all cases reduce the decoder complexity for little to no increase in data redundancy, specifically for higher burst error sizes. In this paper, a new class of single burst error correcting codes are presented with a parallel decoding scheme. The proposed parallel decoding scheme enables high speed decoding. This is particularly useful for memories whose performance is sensitive to read or access latencies. A new construction methodology is presented which enables the proposed codes to be derived from already existing codes so that a single burst error can be corrected.
Keywords
Error Detection, Parallel decoding, Hamming code, BCH code, OLS code
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