Power consumption by multipliers peaks when they are adding up partial products. Numerous adders are used to calculate the sum of the partial products when performing higher-order multiplication. Compressor adders, which can add four, five, six, or seven bits at once, can reduce the need for full adders and half adders, saving space and energy. In this paper, we present a design for a 4-bit multiplier that makes use of a full adder cell and relies on a diffusion input technique involving a full swing gate. By simulating the design in cadence virtuoso using TSMC 65nm models at a supply voltage of 1v and a frequency of 250MHz, we can see how the proposed adder design stacks up against other logic styles for full adders. The simulation results demonstrated that the proposed full adder design consumes less power, occupies less space, and produces a wider range of output voltages than any of the other designs considered

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