Multipliers have a great demand these days due to so many applications. Multiplier is the essential component to perform basic operation which are required in almost every circuit. Usually CMOS is used in designing of multipliers but many other techniques like GDI can be utilized to design which support low power designs. With the increasing conditions on delay, a lot of prominence is being laid on design of quick multiplications. We basically use mathematics of olden times also called vedic mathematics. They are used because they provide fast calculations and make designs uncomplicated. There are 16 sutras out of which “UrdhvaTiryagbhyam” is repeatedly used. The design of a two bit multiplier in 90m technology in cadence virtuoso has been compared with a two bit multiplier made using GDI technique. The design of fundamental components is done in the first part and then they are connected to structurevedic multiplier. The same design can be extended to high bit designs as well. There will be composite design components and many summons to face but if we use vedicmaths we can develop easy designs

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