Here we present a Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer in this study to achieve high on-current and reduced inverter latency at the same time. Electrical properties of the proposed Tunnel FET are examined using technology computer-aided design (TCAD) simulations with calibrated tunnelling model parameters in order to investigate the proposed Tunnel FET. The symmetric spacer is used to examine the effect of spacer values on tunnelling rate. The on-current increases as the spacer value increases because the fringing field via the spacer increases tunnelling probability. On the drain side, however, the fringing field through the drain-side spacer boosts ambipolar current and gate-to-drain capacitance, lowering leakage and switching responsiveness.

Tunnel FET; high-κ spacer; subthreshold swing; band-to-band tunneling