The integration of FinFET and GnrFET technology in adders offers significant advancements in high-performance computing applications, particularly in fields requiring high-speed and low-power arithmetic operations such as signal processing, cryptographic computations, and artificial intelligence. Traditional CMOS-based adders face limitations in scaling, power dissipation, and leakage currents, which are critical challenges in the era of nano-scale integrated circuits. To address these issues, this study proposes a novel design and implementation of dynamic path auto-configurable adders utilizing FinFET and GnrFET technologies. The methodology involves designing adders with adaptive path configurations that can dynamically select the optimal path based on the operational requirements, thereby enhancing performance and energy efficiency. The FinFET-based design leverages the superior electrostatic control and reduced short-channel effects, while the GnrFET-based design exploits the high carrier mobility and ballistic transport properties. The proposed adders are evaluated through extensive simulations, demonstrating significant improvements in speed, power consumption, and area efficiency compared to conventional CMOS adders. This approach not only mitigates the existing problems associated with scaling and power inefficiency but also paves the way for future advancements in low-power, high-speed computational architectures.

dynamic path auto-configurable adders, high-performance computing, low-power design, nano-scale integrated circuits, power dissipation, leakage currents, computational architectures.