Volume 20 No 20 (2022)
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Design of 16x16 Vedic multiplier for fast DCT computation using 45nm Technology
SINDHU R, Dr. ROHITHA UJJINIMATH
Abstract
Digitizing a natural image or conversion from time domain to frequency domain require transformation of the analog data. Discrete Cosine Transform is one of the many methods available for transformation. DCT is extensively computational with many multiplier and adder units. Its known fact that multiplier block consumes more power and for battery powered portable devices an alternative algorithm is to be used which supports low power vlsi. And if we look back to our ancient heritage of math’s, Vedic mathematics becomes a boon to design DCT. Computational steps are reduced in Vedic multiplier. A comparative study is done between 16x16Vedic multiplier and Booth multiplier which are implemented using ISE design suite 14.7with area and power report generated cadence 45nm technology.
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