Based on the concept of band-to-band tunneling, tunnel FETs (TFETs), which have lower leakage current and a sub-threshold slope than MOSFETs, are discovered to be a promising option for extremely low power electronic applications. But it's crucial to examine how these devices perform in analog and digital circuits in comparison to traditional MOSFETs. Since TFETs are currently only used in research, circuit simulators do not include built-in models for these devices, making it impossible to simulate circuits using TFETs. The objective of this work is to use Verilog-A to integrate an analytical model of TFET based on physics into the Cadence build framework, and to use the integrated model to build and simulate digital circuits. In Cadence, a library containing all fundamental TFET-based logic gates is produced. A library is created in Cadence which includes all basic logic gates based on TFET using which half adder circuits are realized. The proposed Tunnel FET based full adder device has recommended ate for first-rate potential as a capable contender for replacing MOSFET in low-energy, high-performance applications such as Tunnel FET based Biosensor for Health-IoT Applications.

TFET, Leakage power, Reliability, Band to Band tunnelling, adder