Volume 20 No 12 (2022)
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Energy- and Area-Efficient VLSI Architecture based MMSE Detector for Massive MIMO Systems
Manasa M Dr. Thanuja T C
This paper presents a VLSI implementation based MMSE Detector for massive MIMO system scheme for low power. Minimum-mean-square-error (MMSE) detection is increasingly relevant for massive multiple-input multiple-output (MIMO) systems. MMSE suffers from high computational complexity and low parallelism because of the increasing number of users and antennas in massive MIMO systems. The current implementation is based architecture design to iteratively estimate signals. First, a recursive conjugate gradient detection algorithm is proposed that achieves high parallelism and low complexity through iteration. Second, a quadrant-certain-based initial methodthat improves detection accuracy without added complexity is proposed. Third, an approximated log likelihood ratio (LLR) computation method is proposed to achieve simplified calculation. The analyses show that compared with related methods, the proposed RCG algorithm reduces computational complexity and exploits the potential parallelism. RCG is mathematically demonstrated to achieve low approximated error. Based on the RCG method, architecture is proposed in 64-QAM massive MIMO system. The massive MIMO system is designed, implemented and tested in 45nm technology for synthesis and simulation results were carried out from Xilinx 14.3. The proposed architecture with MMSE detector technique has 54 numbers in logic gates and consumes 252 nw in a power dissipation and minimum area of 2010nm.
Massive multiple-input multiple-output (MIMO), detection, very-large-scale integration (VLSI), wireless communications
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