This dissertation design focuses on the creation and study of stationary arbitrary access memory (SRAM) cells employing nanoscale technology. With advancements in semiconductor manufacturing methods, the integration of nanoscale transistors in SRAM cells is now generally possible. The purpose of this research is to investigate the hidden benefits and obstacles of applying nanoscale technology in SRAM cells. The research starts with a review of SRAM cell architecture and the typical CMOS technology employed in its creation. It also digs into emerging nano-scale technology, highlighting its benefits such as higher density, lower power consumption, and improved device performance. The investigation also includes an examination of the nanoscale transistors and other components commonly employed to improve SRAM cell performance. To assess the efficacy of nano-scale technologies. In SRAM cells, a comparative analysis will be performed between typical CMOS-grounded SRAM cells and nano-scale SRAM cells in terms of several performance parameters such as speed, power consumption, area application, and trustability. Simulations and experiments will be used to assess the performance criteria using industry-standard tools and procedures. Similarly, this investigation will look at the effect of nano-scale technology on SRAM cell stability, taking into account colorful process changes, temperature goods, and leakage currents. The project will also look at the viability of using novel design techniques like FinFETs and nanowire transistors to improve cell stability and minimize leakage. The outcomes of this investigation will help to better understand the benefits and limitations of using nanoscale technologies in SRAM cell design. Future developments in nano-scale SRAM cells will be facilitated by the findings, which will enhance memory systems' effectiveness and performance in a range of applications, including high-performance computing, mobile bias, and IoT bias. This study examines SRAM cell evaluation at nanotechnology using tunnel FETs. To summarize, tunnel FETs, or TFETs for short, are semiconductors with all the characteristics required to function as transistors in circuits with stringent specifications, such as those found in Internet of Things (IoT) and biomedical applications. Specifically, the Gate-All-Around (GAA) FET device architecture provides better gate junction control throughout the channel and an improved ION/IOFF ratio. The main goal of this work is to determine whether using the GANTLET circuit architecture to build dependable, low-power SRAM memory cells is feasible. The consistency In this study, n-type and p-type tunnel FET devices are designed and tested using the Cogency Visual TOAD tool. Using lookup tables obtained from device modeling, a Verilog-A model was created for circuit simulations of 6T and 8T SRAM cells.

stationary arbitrary access memory( SRAM), nano- scale technology, CMOS, transistors, accoutrements , performance criteria , stability, process variations, leakage currents, FinFET, nanowire transistors, SRAM Cells, Using Tunnel FET Nanoscale or Nanotechnology.