Volume 20 No 12 (2022)
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FPGA Based Register Access and Memory Control for 5G Beamforming Processing
Rakshitha M , Shivaputra , Girish Prabhu , Chooppakatla Venkata Naveen Kumar
The Evolution of radio communication during the last decades has brought major improvements in exploring new types of architecture and technologies to meet the growing demands of the consumer. A fifth generation (5G) network, actively standardized by 3GPP under Release 15, exploits the millimeter wave frequencies to dramtically increase the network bandwidth. Typically, in 5G communication such high frequencies is carried out by newer frequency bands with a wider bandwidth. Besides continous improvements in terms of data capcity, a technique called beamforming is brought up which is distinguishable feature from the previous generations. In the current approach, we design 4T8R macro O-RU to implement beamforming which extracts the beam weights generated by ODU and sent via C-plane packets, and the address calculation to store the beam weights is calculated with respect to the beam ID. O-RU needs to fetch the beam weights associated with that beam ID from the internal memory. The beam ID serves as a pointer to read from beam weight memory and performs complex multiplication and addition of those to indicate which beam to be applied for further processing. The proposed design is carried out using Verilog HDL and delivered using the Xilinx Vivado Tool and this design is tested on the Xilinx Zynq ZCU102 board which demonstrates that our implementation achieves the IQ data extracted from the C-plane packets and obtains the high gain beam intended for the specific user
Beamforming, beam ID, beam weights, mmWaves
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