This paper introduces a novel data scaling technique designed to minimize truncation errors in fixed- width Booth multipliers (FWBMs). By reducing the number of redundant bits in the multiplicand, our proposed technique optimizes bit allocation in low-error FWBMs. To further mitigate truncation errors, we incorporate an error-compensation circuit into the multiplier architecture. Our results show that the signal-to-noise ratio of the proposed data scaling technique combined with a 1-bit FWBM (DST-FWBM) exceeds that of a conventional FWBM by over 2.05 dB. Moreover, our long-width DST-FWBMs achieve accuracy levels approaching those of ideal post-truncated multipliers. We validate the performance of our DST-FWBM by implementing it in a 45nm CMOS process. The proposed data scaling method significantly enhances the accuracy of FWBMs, making it a suitable technology for digital signal processing applications.

Fixed-width Booth multiplier (FWBM), Truncation error, Data scaling technology (DST), VLSI