A network-on-chip (NoC) improves the technology and the power dissipated starts to opposed with by the additional elements of the correspond ion subsystem. Sample adaptive encoder architecture has been acquired as a new in-loop filtering block. To get the optimum AO parameters exhaustive operations are required because of the huge amount of samples. In this paper, High speed and low power Proposed Encoder Decoder of rate ½ convolutional coding with a constraint length K = 3 is presented. A high speed it also maintain a low delay in Spartan 6 FPGA. Since the FPGA boards used are different and from that we justified that using both logics together in one Integrated Circuit (IC) we can create a high speed and low power Proposed encoder decoder at the same time with some extra hardware area.

Network on chip[NOC], Adaptive offset[AO], Integrated Circuit [IC]