Fractional-order differentiation and integration processes are significant aspects of fractional-order calculus, which is generally applied in signal processing. The design complexity of the numeric designs essential in an approximation of fractional-order differentiators/integrators is indeed a unique feature of fractional-order differentiators/integrators. Current techniques suffer from this obstacle and require more power consumption. This paper presents a basic structure that simulates fractional-order differentiators and integrators, composed of 10 NMOS, 11 PMOS transistors, and three DC sources. The proposed scheme has been implemented in a monolithic form with the electronic tuning capability to reduce the inaccuracy in frequency response. The realization of the circuit has been simulated using the Cadence 180nm CMOS process.

Integrator, Differentiator, Fractional order capacitor, Current mirror