Due to the increasing number of people using computers, laptops, mobile phones, and tablets, there is a greater need for devices with increased power efficiency, speed, compactness, and energy efficiency. To satisfy customer expectations, it is imperative that we as engineers, designers, and developers take these characteristics into consideration. There are several different adder design styles available, including carry increment adders, carry save adders, carry bypass adders, carry look-ahead adders, carry select adders, carry skip adders, and ripple carry adders. The calculation speed of the Ripple carry adder is restricted despite its compact design. Carry look-ahead and Carry select adders, on the other hand, provide better performance. The design of integrated circuits (ICs) that are high-speed, low-power, and space-efficient requires careful consideration of factors such occupied area, power consumption, and delay time. To lower power consumption and increase performance speed, many logic styles are used, such as pass transistor logic (PTL), dual rail domino logic, dynamic CMOS, pseudo NMOS, and static CMOS. The Gate Diffusion Input (GDI) methodology is a very effective method for lowering transistor counts, propagation delays, and power consumption in digital circuits as compared to other approaches. PTL logic does, however, present some problems with output deterioration. In order to circumvent these obstacles, the logic gates required to create a Carry look-ahead adder are purposefully designed using the GDI technique. The objectives of this strategy are minimal transistor counts, low power consumption, short latency times, and energy economy.

Adders, Carry Look-Ahead Adder, PTL, CMOS, GDI, Tanner EDA, Low-Power IC Design, High-Speed Performance, Energy Efficiency.