Volume 20 No 6 (2022)
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SYSTEM VERILOG ASSERTIONS FOR THE AHB PROTOCOL VERIFICATION
Dr. VijayN. Patil, Prof. Sudhir N. Divekar, Dr. Sanjivan N. Mahadik, Prof. Mohan D. Dhagate
Abstract
Increasing technology is increasing the amount of logic that can be placed in a silicon chip, driving the development of highly integrated SoC designs. The most important factor for an SoC is how well they are interconnected. The SoC uses an on-chip bus architecture. AMBA (Advanced Microcontroller Bus Architecture) is the most widely used on-chip bus introduced by ARM. 85-90% of the on-chip bus used in a SoC is AMBA (Advanced Microcontroller Bus Architecture). In this work, a AMBA AHB bus verification environment is created and verified using System Verilog Assertions. AMBA Protocol (AHB) is verified by performing successful reads and writes for incremental bursts. Simulation of the AHB verification environment is performed using the Questa Simulator tool (from Mentor Graphics).
Keywords
AMBA ,AHB ,SV,SVA.
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