This research focuses on the design and implementation of a multi-core processor with a tile structure and transactional memory method to improve resource utilization and address the limitations of hardware transactional memory systems. The proposed processor utilizes a network-on-chip to connect the tiles, and the number of each tile type can be adjusted based on application requirements. In this architecture, L2 cache is bypassed during transaction execution, and a router on the chip efficiently routes and stores transaction read-write requests in a transaction buffer area. A partition strategy is employed to allocate a portion of the available region specifically for transaction threads, and the read-write operations of transactions are recorded in the transaction buffer area. Furthermore, the size of the partition dynamically expands as the transaction read-write set increases. Through these innovations, the research aims to address issues related to resource waste, low buffer area utilization, and lack of support for thread switching and migration. The effectiveness of the proposed design is evaluated through simulations and benchmarking, demonstrating its ability to mitigate transaction buffer overflow and enhance overall performance.

Multi-core processor, tile structure, transactional memory, resource utilization, network-on-chip, partition strategy, buffer area, thread switching, migration, performance optimization.