This paper discusses the design and analysis of Software Phase Locked Loop (SPLL). The study of phase-locked loops (PLLs) has been extensively covered in the literature, and most of its theoretical and analytical results are verified by simulations on a PSpice (16.6 version). The SPLL algorithm is implemented on a 32-bit floating point Digital Signal Processor (DSP), using a C6713 simulator from Texas Instruments. The most of the program is shared between the acquisition of the input signal using two external hardware interrupt routines, the SPLL processing, and the graphical representation of the results on Matlab (7.1 version) based on a Real Time Data Exchange (RTDX). Some results are analyzed and validate the associated theoretical results on the implemented system. The gradual optimization of the code, going through C, then linear assembly, to accomplish our work with pure assembly, allows real-time SPLL processing under increasingly high input frequencies.

Phase Locked Loop (PLL), Software Phase Locked Loop (SPLL), Digital Signal Processor (DSP), Code Composer Studio (CCS), Texas Instruments (TMS), Real Time Data Exchange (RTDX).